The testing of integrated circuits can occur throughout the life of a device. An integrated circuit may be tested in die form, while still part of a wafer, in packaged form at the “back” end of a manufacturing process, and/or after the device has been incorporated into a system (“in system” testing).
Self-test can increase the speed at which a device is tested, as an integrated circuit can typically operate at a faster speed than a tester. Moreover, built-in self-test (BIST) circuits can incorporate more complex test functions on the device itself, which can reduce or eliminate the need for expensive complex tester equipment.
While self-test can perform an important function in screening new devices, self-test can also perform an important function once a device is in system. If a defective device is properly diagnosed by a self-test, the device can include built-in self-repair (BISR) circuits for repairing the device. Unfortunately, such an approach is typically only possible for relatively simple devices, as conventional BIST circuits for more complex device do not provide sufficient test “coverage”. That is, a self-test may not be thorough enough, or test enough features/combinations of a device to adequately determine the location and/or type of defect.
Due to the complexity of many integrated circuits, it may be desirable to apply a number of test patterns (e.g., vectors) to self-test circuits, such as scan chains. Multiple test patterns can be generated by a tester and applied to a device. However, even with very expensive high speed testers, such an approach may take considerable time and/or not apply such values at the clock speed (e.g., normal operating speed) of the integrated circuit.
One conventional approach to generating test patterns at clock speed is to include a “built-in” test pattern generator on a device. That is, a test pattern generator can be included in the integrated circuit substrate and/or the package of the integrated circuit. In order to apply a wide variety of test pattern at a rapid speed, such a built-in test pattern generator can be a pseudo-random pattern generator (PRPG). Conventional PRPGs typically utilize a linear feedback shift register (LFSR).
A conventional PRPG can operate according to seed values (or “seeds”). Seed values can be initial patterns from which a series of subsequent test patterns can be generated. A test coverage can thus depend upon the number of seed values that are applied to a PRPG.
At the same time is it desirable to generate test patterns in a rapid fashion, it is also desirable to capture self-test results in a rapid pattern. One conventional approach for capturing test results at clock speed is to include a “built-in” output register. In order to capture output data in a rapid fashion, conventional BIST circuits can employ a multiple-input signature register (MISR). An MISR can compress multiple output pattern results in to a “signature” for subsequent readout/comparison with an expected “good” signature (a signature corresponding to properly functioning device).
To better understand the various features of the embodiments of the present invention, conventional BIST approaches will now be described in more detail.
Referring now to FIG. 8, a conventional BIST section of an integrated circuit is set forth in block diagram and designated by the general reference character 800. A BIST section 800 can include a “core” logic portion 802 that can be self-tested. One or more scan chains (804-0 to 804-n) and be included in, or associated with, a core logic portion 802. As is well understood, scan chains (804-0 to 804-n) can deliver test patterns to, and output test data from, a logic portion 802 to thereby test the operation of the logic portion 802.
The BIST section 800 of FIG. 8 includes a PRPG 806 that can receive test seed values from a test input 808, and generate test patterns for propagation down scan chains (804-0 to 804-n). An MISR 810 can receive values from scan chains (804-0 to 804-n) and from test input 808 and determine whether a logic portion 802 passes a particular self-test.
As shown in FIG. 8, both a PRPG 806 and MISR 810 can be controlled by a BIST controller 812. A BIST controller 812 can be operated according to control data received at a BIST control input 814.
Referring to now to FIG. 9, an integrated circuit that incorporates a BIST section 800 is shown in a block schematic diagram. An integrated circuit 900 can include at test interface 902 that controls the application of data to a BIST section 800. As but one example, many test interfaces 902 can be serial interfaces to thereby reduce the pin count required for a self-test.
FIG. 10 shows one example of a conventional auto-BIST operation. The method is designated by the reference character 1000 and includes activating an auto-BIST function (1002). Such a step can activate BIST circuits within a device (e.g., PRPG, BIST controller, MISR). A seed value device may then be loaded into the device (1004). Such a step may include loading an inherent seed value by start-up state of a PRPG and/or inputting a seed value from outside the device (e.g., serial shifting in a seed value).
A method 1000 may continue by generating test patterns with the PRPG according to the seed value (1006). According to such test values, a portion of the device (e.g., core logic portion) can be self-tested (1008). An output signature resulting from such a self-test can be captured, for example, by operation of an MISR.
While a conventional auto-BIST approach like that of FIG. 10 may be sufficient for simple devices, such an approach may not be adequate or fast enough for more complex devices. In particular, self-testing from a single seed value may not provide adequate coverage of device functions to properly diagnose/determine fault. However, while it may be possible to input more seed values, this can be very time consuming. Further, such an approach may not permit clock speed testing based on multiple seed values, as the device operation would have to stop between the loading of each seed value.
A second conventional test approach is shown in FIG. 11, and designated by the general reference character 1100. FIG. 11 shows the use of automatic test equipment ATE to provide a high coverage and relatively high speed test for a device like that shown in FIG. 8.
In FIG. 11, ATE 1102 can generate test control values and test data for a BIST section 800 of an integrated circuit. Further, ATE 1102 can include a memory 1104 in which to store multiple seed values. Thus, as a PRPG completes the generation of test patterns based on one seed value, an ATE 1102 can load a next seed value.
A conventional approach like that shown in FIG. 11 can provide wide test coverage by loading multiple seed values. However, such an approach may still not be capable of providing at clock speed testing, as the loading of seed values may still require some time. In addition, such an approach can be costly as ATE equipment and ATE test times can be expensive. Still further, the approach like that shown in FIG. 11, testing by ATE is typically not possible once a device is “in system”.
In light of the above, it would be desirable to arrive at some way of executing a BIST operation in a device that provides wide test coverage at high speeds, but is not as costly as conventional ATE arrangements.
In addition, it would also be desirable to arrive at a BIST approach that is compatible with built-in self-repair for complex integrated circuits.